AMD | Bulldozer (processor)

Bulldozer is the codename AMD has given to one of the next-generation CPU cores after the K10 microarchitecture for the company’s M-SPACE design methodology, with the core specifically aimed at 10 watt to 100 watt TDP computing products. Bulldozer is a completely new design developed from the ground up and is a part of AMD’s K11-series CPU. AMD claims dramatic performance-per-watt improvements in HPC applications with Bulldozer cores.[1]  Products implementing the Bulldozer core are planned for release in 2011.

The Bulldozer cores will support most of the instruction sets currently implemented in Intel processors (including SSE4.1, SSE4.2), future Instruction sets announced by Intel (AES, PCLMULQDQ and AVX), as well as future instruction sets proposed by AMD

As of November 2009, Bulldozer-based implementations built on 32 nm are scheduled to arrive in 2011 for both servers and desktops, as the 16-core Opteron processor codenamed Interlagos and as the 4- or 8-core desktop processor codenamed Zambezi.

The design of Bulldozer is heavily revamped from the previous generation. With Bulldozer, the two 128-bit FMA-capable FPUs can be combined into one 256-bit FPU. This design is accompanied with two integer cores each with 4 pipelines (the fetch/decode stage is shared). AMD calls this design a “Bulldozer module”. A 16-core processor design would feature eight of these modules, but the operating system will see each module as two physical cores.